AccelerComm, a University of Southampton spinout, develops error correction and physical layer IP for 5G, 6G and satellite networks, running on more than 200 satellites. They're hiring a Senior Design Engineer to develop RTL for a 5G base station designed to operate on board satellites, based in Southampton on a hybrid basis. This ASIC role sits within the UK's semiconductor and satellite communications sector.
We are looking for multiple Senior Design Engineers who will work on revolutionary technology that is at the leading edge of non-terrestrial communications, a 5G base station to be deployed on board satellites. This technology will underpin the next generation of mobile standards, giving complete coverage to the entire globe. AccelerComm develops the baseband signal processing technology, using hardware acceleration to generate world-leading error resilience, capacity and power efficiency.
You will work on the latest generation space-qualified devices, delivering standalone IP and integrated IP solutions.
Key Responsibilities
- Work closely with the Algorithm and System Architecture teams to understand requirements and translate them into mirco-architectures for RTL implementations
- Implement designs targeting both FPGA and ASIC using industry standard techniques, including the creation of appropriate testbenches
- Deploy your designs onto the latest FPGA development platforms for validation and system integration
- Actively engage with and adhere to AccelerComm engineering methodology, processes and design techniques, being able to offer improvements to efficiency and quality for both the design flow and the final product
- Collaborate with colleagues across the whole design flow: micro-architecture, design, verification, physical implementation and optimisation for ASIC and FPGA
Skills, Knowledge & Expertise
Essential:
- Expert knowledge of an RTL language (Verilog, SystemVerilog) for complex ASIC/FPGA products
- A strong skillset in delivering digital designs in the ASIC and FPGA industry
- Optimisation of timing and hardware resources for high throughput data or signal processing applications. Experience in power management techniques, synthesis and timing analysis
- Track record in collaborating across teams to produce integrated solutions
- Experience in technical documentation writing – design specifications, user guides, verification plans
- Expert user of EDA tools for simulation and synthesis
Desirable:
- Knowledge of communications signal processing algorithms (such as error correction, equalisation, channel estimation, beamforming)
- Familiarity with the AMBA bus protocols
- Understanding of UVM verification techniques or practical experience using UVM for IP verification
- Experience using C++/SystemC for design modelling and integration
- Experience with high speed interfaces such as PCI-E or JESD
- Knowledge of a scripting language, such as Python
- Knowledge and appreciation of project methodologies across the design lifecycle, including agile and waterfall, requirement capture and traceability
- Experience with AMD FPGAs and the associated design tools or with any EDA’s ASIC backend tools
About AccelerComm
AccelerComm is a Southampton-based semiconductor IP company spun out of the University of Southampton's Electronics and Computer Science department in 2016 by Professor Rob Maunder and Dr Taihai Chen. The company commercialises forward error correction and channel coding algorithms for 5G, 6G, and satellite non-terrestrial networks, with products including high-performance LDPC and POLAR error correction IP. AccelerComm's technology powers over 200 production satellites currently in orbit, with customers including Vodafone, Intel, AMD, and National Instruments. The company raised a total of $52.8M, including a £21.5M Series B in 2023 led by ParkWalk, SwisscomVentures, and Hostplus, and a subsequent $15M round in 2025.
Stage: Series BSouthampton
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